Free PDF Verilog by Example: A Concise Introduction for FPGA Design, by Blaine Readler
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Verilog by Example: A Concise Introduction for FPGA Design, by Blaine Readler
Free PDF Verilog by Example: A Concise Introduction for FPGA Design, by Blaine Readler
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A practical primer for the student and practicing engineer already familiar with the basics of digital design, the reference develops a working grasp of the verilog hardware description language step-by-step using easy-to-understand examples. Starting with a simple but workable design sample, increasingly more complex fundamentals of the language are introduced until all major features of verilog are brought to light. Included in the coverage are state machines, modular design, FPGA-based memories, clock management, specialized I/O, and an introduction to techniques of simulation. The goal is to prepare the reader to design real-world FPGA solutions. All the sample code used in the book is available online. What Strunk and White did for the English language with “The Elements of Style,” VERILOG BY EXAMPLE does for FPGA design.
- Sales Rank: #151199 in Books
- Brand: Brand: Full Arc Press
- Published on: 2011-04-19
- Original language: English
- Number of items: 1
- Dimensions: 9.02″ h x .29″ w x 5.98″ l, .42 pounds
- Binding: Paperback
- 124 pages
- Used Book in Good Condition
Most helpful customer reviews
22 of 24 people found the following review helpful.
Great book for beginners
By S. Osterfeld
I am trying to learn a bit about FPGA’s in my limited spare time, and while I haven’t finished this book yet, my impression is that this is probably the best introduction that I will find. It is concise and yet accessible, and slim rather than overwhelming in volume. Instead of making you walk through vendor-specific setup wizards that implement some CPU analog on your FPGA with the click of a button, this book begins with the most fundamental concepts, rationales, syntax rules, and code examples of FPGA programming in Verilog, building from there. Hindsight is always 20/20, and the author’s express purpose was to utilize his learning experience to write the kind of introductory book that he wished he had had 20 years ago when he started out as a novice. I congratulate him to this approach.
8 of 8 people found the following review helpful.
Hard to pin down, exactly
I know exactly who this book is for (me, among others, about 15 years ago), but I’m still not sure how to describe it. Thar reader is fluent enough with normal programming languages that bits of syntax won’t be a problem – making it that much easier to address the problematic parallelism implicit in HDLs. That reader also has a fair understanding about the bits & bobs of logic design: gates, RAMs, registers, and the like, but maybe never took the second course in logic design.
This book, a companion to Readler’s “VHDL by example,” gives the novice a running start at the other major hardware design language. People on both sides can get pretty het up about which is The One, often along geographic lines (Europe vs. US, East coast vs. West coast). The fact is, though, that you don’t often get to pick. Your employer, your work group or client, the tools and libraries available to you will often make the choice for you. So, it’s best to know both, and Readler’s books treat them with a reasonably even hand.
In the unlikely event that you’re free to choose, it’s a matter of taste. I certainly have my preferences, but they don’t matter much. Verilog reminds a programmer of C – I mean, K&R C, from way back, with all the good and bad that implies. Include files, scopeless macro definition, and uninformative module (or function) prototypes will all look familiar. VHDL, on the other hand, derives consciously from Ada, with all the good and bad that implies. That includes packages (which no one uses), operator overloads (which no one thinks they use, but do), and draconian type checking – something that will cost you a lot of time, but very likely save you even more.
Like its VHDL twin, this gives only the basics, i.e. what you’ll use for about 97% of your HDL coding. Like the other, it introduces test benches – just as well, and just as badly. On the “well” side, it shows the basic structure of a test driver, clock generator, test stimulus and housekeeping. On the “badly” side, it provides inputs but never checks outputs. In industry, your logic might be subjected to nightly regression tests, where a robot controller expects your tests to verify the outputs and give a go/nogo output in machine-readable form. These days, a big logic design includes billions or tens of billions of transistors. Believe me, you won’t do eyeball checks of waveforms on each input and output. Saying “I checked the output and it looked good” simply is not an answer.
And, I have to raise a personal peeve about every HDL book in the world, this included. There are lots of things you can put in the synthesizable payload logic: memories, boolean goodies, registers, and simple arithmetic. There are lots of things you can’t: print statements, mod and div operators, and lots more. The synthesizable can go into your FPGA or anywhere; the un-synthesizable can exist only in your simulation environment. You need both, but you also need to draw a thick black line between the two, and never even think about the simulation-only features when you code your payload logic. No book I’ve seen (this included) emphasizes that distinction, and it’s a huge barrier for many students. That said, this book is no worse than any other I know.
So, it’s basic. It’s very basic. Any competent instructor would get you way past this level in a hurry. But many people, my niece included, don’t have instructors, competent or otherwise. If you’re lifting yourself by your own bootstraps into the esoterica of HDL logic design, this is the best Verilog book I know. You’ll need a lot more to gain strength as a logic designer, but everyone has to start somewhere. Bon voyage!
10 of 11 people found the following review helpful.
Excellent Started Book
This was a great starter book for learning Verilog in the context of FPGA design. I would definitely recommend it for anyone looking to pick up the Verilog language. It takes you from language through simulation. It is not a comprehensive reference, but a nice introductory tutorial.
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